NVIDIA Interview Question for Software Engineer / Developers

Country: United States
Interview Type: Phone Interview

Comment hidden because of low score. Click to expand.
of 6 vote

I have given a rough idea here. Not very clear about specific interrupts at each step. Hope this helps.

1) CPU first fetches the instruction x = 7 from the Instruction cache (when it reads this address in the PC/IR)
2) After decoding and executing the instruction, it sees that, it needs to access the memory location of variable x (which will be a virtual address)
3) Hence it issues a request to the TLB to return the physical address/tag.
Assuming the cache is Virtually indexed, it will parallely calculate the index for this virtual address.
4) Since it's a TLB miss, it accesses the Page table which resides mostly in Memory.
//Not sure what the interrupt here is?
5) But since, the translation is not found, meaning the page for this address is not in RAM, it issues a DMA request to transfer the page from Secondary storage to the RAM. It knows the address of the page on Secondary storage through the vm_area struct for this process, which maintains the location of all the pages.
// This is done in page fault handler. Page fault is raised when this even occurs.
6) Once DMA is complete, the processor is interrupted with this event. It then updates the page table with this entry and also the TLB.
//This would be an I/O interrupt to the processor
7) Once it gets the tag, it checks if that tag matches in the cache.
8) It won't, since cache does not have this entry.
9) Hence it fetches this block (cache block) from memory and places into the cache and restarts the execution.
10) In the MEM phase of the execution pipeline, it writes the value 7 to this location in the cache.

- chandan.jc November 05, 2012 | Flag Reply
Comment hidden because of low score. Click to expand.
of 1 vote

There are 2 cases viz. Swapping/Non-Swapping:

Case 1: No Swapping.
Here we assume, we have physical pages available, hence no swapping needed.
1. CPU fetches the instruction x=7 (We assume, code page is in memory) and decodes it.
2. CPU tries to find corresponding physical address of "x" by looking at TLB. Since there is no TLB entry present, (first stop the instruction) MMU (Memory management unit) raises TLB exception, otherwise know as TLB Fault.
3. Now, TLB fault handling code, visits PTE (Page table entries) to find corresponding physical page. Since, there is no physical page assigned, this causes Page Fault to be raised, which allocates a page in RAM and updates PTE.
4. Restart the instruction.
Note - We havent updated TLB entry yet. This would be done when the restarted instruction runs again, which would again raise TLB fault, but this time TLB fault handling code would find the corresponding physical page and would load the TLB entry and the instruction is restarted.
5. Thus finally, this time, there would be no TLB fault and Page fault and instruction would be successful.

Case 2 - Swapping.
In this case, RAM is out of physical pages and only way to find a physical page is to swap out a used physical page to the HDD and then use that page (the one that we swapped out) to assign during Page fault.

Rest remains the same. Only, Page Fault handling changes i.e. it involves swapping (HDD is involved). Note - We also need to update PTE of the page we swapped out to the disk, so that the process (whose page we swapped out ) knows about its page location.

- Anonymous May 23, 2013 | Flag Reply

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