## NVIDIA Interview Question for Software Engineer / Developers

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1
of 1 vote

Maximum burst 80 wordsf followd by 20 idle cycles
clock period write: 250Mhz

1) The write takes 320ns to write 80 words followed by 20 idle cycles.
3) 400-320-=80 write overtakes read by this magnitude.
4) Then we have 80/5 = 16 cycles for read to catch up. --> Depth needed so write does not over run read

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0

I would replace 2-4 steps with the following:

2) In the 320ns, we can clear reading 320/5=64 words
3) We need 80-64=16 words in buffer

Sanity check:
20 idle write cycle are 80 ns which are 16 read cycles --> we manage to clear the FIFO for next burst

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0
of 0 vote

32 words

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0

Can you explain how you got 32 words?

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0
of 0 vote

4ns isn't a speed. speed is operations / time. What are you try saying?

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0
of 0 vote

Question is incomprehensible to me.. if anyone can understand it I would be grateful if he could explain it to me

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0

The worst case is that it can write 160 words consecutively. The time of writing is (160*4)ns. Reading is one word per cycle. So the number of reading is 160*4/5=128. Therefore, we need 160-128=32.

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0
of 0 vote

The worst case is that it can write 160 words consecutively. The time of writing is (160*4)ns. Reading is one word per cycle. So the number of reading is 160*4/5=128. Therefore, we need 160-128=32.

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0
of 0 vote

The worst case FIFO depth is at 320ns when the burst has been just completed. At that time the read stands at 320*(80/415) = 61.69 between 61 and 62 words. You have to consider that at 415ns the entire FIFO will have been read and not 400ns. This is because for an async FIFO the synchronizer will have a maximum latency of 3 cycles (1 for meta-stable and two flop delays in worst case) and each cycle is 5ns.
So at 320ns time, the read would have only read 61 words. Therefor my FIFO has to cover for the extra 80-61=19 words. So the FIFO is of depth 19.

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