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Suppose we have two CPUs, each has an L1 cache associated with it. An L2 cache is shared by the two CPUs, and it requests data from DRAM:

|CPU0| |CPU1|
|L1Cache0| |L1Cache1|
|Shared L2C|
|DRAM|

Let's say CPU0 and CPU1 send out a write signal at the same time:

- At timestamp 0, CPU0 sends a wr request - write address A to 0;
- Also at timestamp 0, CPU1 sends a wr request - write address A to 1;
- At timestamp 0, all of the L1/L2 caches are empty, i.e. write req will result in a miss in the cache;
- At timestamp 0, data in address A in DRAM is 100;
- Cache coherency protocol is MOESI.

What will the values be after these two writes complete? In L1, L2 and DRAM? and what are the states in each cache?