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wikipedia.org/wiki/CPU_cache#2-way_set_associative_cache

wikipedia.org/wiki/CPU_cache#2-way_set_associative_cache

wikipedia.org/wiki/CPU_cache#2-way_set_associative_cache

If each location in main memory can be cached in either of two locations in the cache, one logical question is: which two? The simplest and most commonly used scheme, shown in the right-hand diagram above, is to use the least significant bits of the memory location's index as the index for the cache memory, and to have two entries for each index. One benefit of this scheme is that the tags stored in the cache do not have to include that part of the main memory address which is implied by the cache memory's index. Since the cache tags have fewer bits, they take less area on the microprocessor chip and can be read and compared faster. Also LRU is especially simple since only one bit needs to be stored for each pair.